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MSC23409C/cl-xxds9 ? semiconductor 1/13 ? semiconductor MSC23409C/cl-xxds9 4,194,304-word 9-bit dram module : fast page mode type description the oki MSC23409C/cl-xxds9 is a fully decoded 4,194,304-word 9-bit cmos dynamic random access memory module composed of nine 4-mb drams (4m 1) in soj packages mounted with nine decoupling capacitors on a 30-pin glass epoxy single-inline package. this module is generally used for memory expansion in parity applications such as workstations. the low-power version (cl) offers reduced power consumption for mobile computing applications like laptops and palmtops. features ? 4-meg 9-bit organization ? 30-pin socket insertable module MSC23409C/cl-xxds9 : solder tab ? single 5 v supply 10% tolerance ? access times : 60, 70, 80 ns ? input : ttl compatible ? output : ttl compatible, 3-state ? refresh : 1024 cycles/16 ms (128 ms : l-version) ? cas before ras refresh, cas before ras hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? fast page mode capability product family family access time (max.) cycle time (min.) power dissipation operating (max.) standby (max.) t rac t aa t cac MSC23409C/cl-60ds9 MSC23409C/cl-70ds9 MSC23409C/cl-80ds9 60 ns 70 ns 80 ns 30 ns 35 ns 40 ns 15 ns 20 ns 20 ns 110 ns 130 ns 150 ns 4950 mw 4455 mw 3960 mw 49.5 mw/ 9.9 mw (l-version) e2h0093-15-90 this version: sep. 1995
MSC23409C/cl-xxds9 ? semiconductor 2/13 pin configuration MSC23409C/cl-xxds9 typ. 10.16 typ. 6.35 82.14 typ. 3.38 tpy. 88.9 ?.2 73.66 2.03 typ. 1.27 +0.1 ?.08 5.28 max. 2.54 ?.1 30 1 * 1 *1 the common size difference of the board width 12.5 mm of its height is specified as ?.2. the value above 12.5 mm is specified as ?.5. 20.45 max. 5.59 typ. 1.78 typ. 2.54 min. f 3.18 v cc pin name cas dq0 a0 a1 dq1 a2 a3 v ss dq2 a4 pin name a5 dq3 a6 a7 dq4 a8 a9 a10 dq5 we pin name v ss dq6 nc dq7 q8 ras cas8 d8 v cc pin no. 1 2 3 4 5 6 7 8 9 10 pin no. 11 12 13 14 15 16 17 18 19 20 pin no. 21 22 23 24 25 26 27 28 29 30
MSC23409C/cl-xxds9 ? semiconductor 3/13 block diagram a0 - a10 ras0 cas0 we v cc v ss c1 c9 ras cas we v cc dq0 a0 - a10 d q v ss ras cas we v cc dq1 a0 - a10 d q v ss ras cas we v cc dq2 a0 - a10 d q v ss ras cas we v cc dq3 a0 - a10 d q v ss ras cas we v cc dq4 a0 - a10 d q v ss ras cas we v cc dq5 a0 - a10 d q v ss ras cas we v cc dq6 a0 - a10 d q v ss ras cas we v cc dq7 a0 - a10 d q v ss ras cas we v cc q8 a0 - a10 d q v ss d8 cas8
MSC23409C/cl-xxds9 ? semiconductor 4/13 electrical characteristics absolute maximum ratings note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions capacitance voltage on any pin relative to v ss parameter symbol rating unit v in , v out ?.0 to 7.0 v voltage v cc supply relative to v ss v cc ?.0 to 7.0 v short circuit output current i os 50 ma power dissipation p d 9w operating temperature t opr 0 to 70 ? storage temperature t stg ?0 to 125 ? parameter symbol unit power supply voltage v cc input high voltage typ. min. max. 4.5 5.0 5.5 v (ta = 0? to 70?) v ss 000v v ih 2.4 6.5 v v il ?.0 0.8 v input low voltage parameter symbol unit c in1 pf input capacitance (a0 - a10) typ. max. ?4 (ta = 25?, f = 1 mhz) c in2 pf input capacitance ( ras , cas , we )73 c in3 pf input capacitance ( cas8 )13 c in4 pf input capacitance (d8) 12 c out pf output capacitance (q8) 13 c dq pf i/o capacitance (dq0 - dq7) 19 note : capacitance measured with boonton meter.
MSC23409C/cl-xxds9 ? semiconductor 5/13 dc characteristics notes: 1. specified values are obtained with the output open. 2. address can be changed once or less while ras =v il . 3. address can be changed once or less while cas =v ih . 4. v cc - 0.2 v v ih 6.5 v, -1.0 v v il 0.2 v. 5. l-version. all other pins not parameter MSC23409C/cl MSC23409C/cl unit condition MSC23409C/cl input leakage current note i li ? 1, 2 min. ?0 max. 90 min. ?0 max. 90 min. ?0 max. 90 (v cc = 5 v ?0%, ta = 0? to 70?) symbol 0 v v i 6.5 v; under test = 0 v d out disable 0 v v o 5.5 v i oh = ?.0 ma i ol = 4.2 ma ras , cas cycling, t rc = min. ras , cas = v ih ras , cas 3 v cc ?.2 v ras cycling, cas = v ih , t rc = min. ras cycling, cas before ras , t rc = min. ras = v il , cas cycling, t pc = min. t rc = 125 ?, cas before ras cycling output leakage current output high voltage output low voltage average power supply current (operating) power supply current (standby) supply current ( ras -only refresh) average power supply current ( cas before ras refresh) average power supply current (fast page mode) average power supply current (battery backup) average power i lo v oh v ol i cc1 i cc2 i cc3 i cc6 i cc7 i cc10 ? ?0 10 ?0 10 ?0 10 v 2.4 v cc 2.4 v cc 2.4 v cc v 0 0.4 0 0.4 0 0.4 ma 900 810 720 ma 18 18 18 ma ?99 ma 1.8 1.8 1.8 ma 900 810 720 ma 900 810 720 ma 720 630 540 ma 2.7 2.7 2.7 1 1 1, 5 1, 2 1, 2 1, 3 4, 5 1, 2 -60ds9 -70ds9 -80ds9
MSC23409C/cl-xxds9 ? semiconductor 6/13 ac characteristics (1/2) parameter symbol MSC23409C/cl MSC23409C/cl unit min. max. MSC23409C/cl random read or write cycle time min. max. min. max. note (v cc = 5 v ?0%, ta = 0? to 70?) note 1,2,3,9,10 t rc 110 130 150 ns 4, 5, 6 fast page mode cycle time t pc 40 45 50 ns 70 access time from ras t rac ?0 ?0ns 20 access time from cas t cac ?5 ?0ns 35 access time from column address t aa ?0 ?0ns 40 access time from cas precharge t cpa ?5 ?5ns output low impedance time from cas t clz 00 0ns 20 output buffer turn-off delay time t off 0150 020ns 50 transition time t t 3503 350ns 16 refresh period t ref ?6 ?6ms 128 refresh period (l-version) t ref 128 128 ms ras precharge time t rp 40 50 60 ns 10k ras pulse width t ras 60 10k 70 80 10k ns 100k ras pulse width (fast page mode) t rasp 60 100k 70 80 100k ns ras hold time t rsh 15 20 20 ns cas precharge time t cp 10 10 10 ns 10k cas pulse width t cas 15 10k 20 20 10k ns cas hold time t csh 60 70 80 ns cas to ras precharge time t crp 55 5ns 50 ras to cas delay time t rcd 20 45 20 20 60 ns 35 ras to column address delay time t rad 15 30 15 15 40 ns row address set-up time t asr 00 0ns row address hold time t rah 10 10 10 ns column address set-up time t asc 00 0ns column address hold time t cah 15 15 15 ns column address hold time from ras t ar 50 55 60 ns column address to ras lead time t ral 30 35 40 ns 4, 5 4, 6 4 4 7 3 5 6 -60ds9 -70ds9 -80ds9
MSC23409C/cl-xxds9 ? semiconductor 7/13 ac characteristics (2/2) parameter symbol MSC23409C/cl MSC23409C/cl unit min. max. MSC23409C/cl read command set-up time min. max. min. max. note t rcs 00 0 ns 8 (v cc = 5 v ?0%, ta = 0? to 70?) note 1,2,3,9,10 read command hold time t rch 00 0 ns read command hold time referenced to ras t rrh 00 0 ns write command set-up time t wcs 00 0 ns write command hold time t wch 10 10 10 ns write command hold time from ras t wcr 45 50 60 ns write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 15 20 20 ns write command to cas lead time t cwl 15 20 20 ns data-in set-up time t ds 00 0 ns data-in hold time t dh 15 15 15 ns data-in hold time from ras t dhr 50 55 60 ns cas active delay time from ras precharge t rpc 55 5 ns ras to cas set-up time ( cas before ras )t csr 55 5 ns ras to cas hold time ( cas before ras )t chr 10 10 10 ns cas precharge time (refresh counter test) t cpt 30 35 40 ns we to ras precharge time ( cas before ras ) t wrp 10 10 10 ns we hold time from ras ( cas before ras )t wrh 10 10 10 ns ras to we set-up time (test mode) t wts 10 10 10 ns ras to we hold time (test mode) t wth 10 10 10 ns 8 -60ds9 -70ds9 -80ds9
MSC23409C/cl-xxds9 ? semiconductor 8/13 notes: 1. a start-up delay of 200 m s is required after power-up followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. when using the internal refresh counter, a minimum of eight cas before ras initialization cycles is required. 2. ac mesurement assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times are measured between v ih and v il . 4. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, access time is controlled by t aa . 7. t off (max.) defines the time at which the output achieves an open circuit condition and is not referenced to output voltage levels. 8. t rch or t rrh must be satisfied for a read cycle. 9. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. the test mode specified in this data sheet is an 8-bit parallel test function. ra10, ca10 and ca0 are not used. in a read cycle, if all internal bits are equal, the data output pin will indicate a high level. if any internal bits are not equal, then data output pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operational state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 10. in a test mode read cycle, the access time parameters are delayed by 5 ns. the test mode parameters are obtained by adding 5 ns to the normal read cycle values.
MSC23409C/cl-xxds9 ? semiconductor 9/13 ras address we dq0-7 v ih v il v ih v il e e v ih v il e e v ih v il e e v oh v ol e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t rad t ral t asr t rah t asc t cah row column t ar t rcs t rch t rrh t cac t aa t clz t rac t off open valid data-out "h" or "l" cas cas8 q8 write cycle (early write) ras address we v ih v il v ih v il v ih v il v ih v il "h" or "l" v ih v il e e t rc t ras t rp t csh t crp t rcd t rsh t crp t cas t ar t rad t ral t rah t asr t asc t cah row column t cwl t wcr t wcs t wch t rwl t dhr t ds t dh valid data-in t wp cas cas8 dq0-7 d8 note: q8 = "open" timing waveform read cycle
MSC23409C/cl-xxds9 ? semiconductor 10/13 fast page mode read cycle fast page mode write cycle (early write) ras address we v ih v il v ih v il v ih v il v ih v il "h" or "l" v ih v il e e t rasp t rp t crp t rcd t cas t cp t pc t cas t cp t cas t rsh t crp t ar t asr t rah t asc t cah t asc t cah t asc t cah t ral row column column column t wcr t wcs t wch t wcs t wch t wcs t wch t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in t dhr t wp t cwl t wp t wp t cwl t cwl t rwl cas cas8 dq0-7 d8 t csh note: q8 = "open" ras address we v ih v il v ih v il v ih v il v ih v il v oh v ol "h" or "l" t rasp t rp t csh t crp t rcd t cas t cp t pc t cas t cp t rsh t cas t crp t ar t asr t rah t asc t cah t asc t cah t ral t asc t cah row column column column t rad t rcs t rch t rcs t rch t rcs t rrh t rch t cac t aa t rac t cac t aa t cpa t cac t aa t cpa valid data-out valid data-out valid data-out t clz t off t clz t off t clz t off cas cas8 dq0-7 q8
MSC23409C/cl-xxds9 ? semiconductor 11/13 ras -only refresh cycle ras address v ih v il v ih v il v ih v il v oh v ol "h" or "l" t rc t rp t ras t rpc t crp t rah t asr row open note: we = "h" or "l" t off cas cas8 dq0-7 q8 cas before ras refresh cycle v ih v il ras v ih v il t rp t ras "h" or "l" v oh v ol t rpc v ih v il open we t rc t wrh t wrp t rpc t wrp t cp t csr t chr t off note: address = "h" or "l" cas cas8 dq0-7 q8
MSC23409C/cl-xxds9 ? semiconductor 12/13 hidden refresh read cycle t asr row column v ih v il ras address v ih v il v ih v il t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ar t ral t chr t ras t wrh t wrp we v ih v il v ih v il "h" or "l" valid data-in t ds t dh t rwl t wp t dhr t wch t wcs t wcr cas cas8 dq0-7 d8 note: q8 = "open" hidden refresh write cycle t asr row column v ih v il v ih v il v ih v il v ih v il t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ar t ral "h" or "l" v oh v ol e e t rrh t rcs valid data-out t rac t aa t off t clz t chr t ras t wrh t wrp t cac ras address we cas cas8 dq0-7 q8
MSC23409C/cl-xxds9 ? semiconductor 13/13 cas before ras refresh counter test cycle v ih v il ras address v ih v il v ih v il t ras t asc t cpt t rsh t cah t cas we v ih v il q8 "h" or "l" v oh v ol e e valid data-in t ds t dh t wp t cwl t wcs t rp v oh v ol valid data-out open t ral t aa t off t cac t clz t wrp open t rrh t wrh t rcs we v ih v il v ih v il t wrp t rwl t wch t rch t wrh read cycle write cycle t chr t csr column cas cas8 dq0-7 q8 dq0-7 d8 v ih v il ras cas cas8 v ih v il t ras "h" or "l" v oh v ol v ih v il open t rc t wth t rpc t wts t cp t csr t chr t off note : address = "h" or "l" t rp we dq0-7 q8 we ? cas before ras refresh cycle

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